Digital comparison element



Jan. 9,1968 D. PETZOLD 3,363,233

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Ww m w We) I w/w Ww Inventor :DiekF-Pebdd ATI'ORNEYS United States Patent 3,363,233 DIGITAL COMPARISON ELEMENT Dieter Petzold, Berlin-Neukolln, Germany, assignor to Licentia Patent-Verwaltungs-GmbH, Frankfurt am Main, Germany Continuation of application Ser. No. 360,649, Apr. 17, 1964. This application Feb. 2, 1967, Ser. No. 613,686 Claims priority, application Germany, Apr. 22, 1963, L 44,690, L 44,691 1 Claim. (Cl. 340146.2)

This application is a continuation of application Ser. No. 360,649 filed Apr. 17, 1964, now abandoned.

The present invention relates to a digital comparison element. Such a comparison element is a circuit component which is used, for various purposes, in digital con trol and computing systems whenever two binary numbers, a and b, are to be compared in order to establish whether these two numbers are equal to each other or, if they are unequal, the algebraic sign of their difference. The numbers are, for example, represented by direct current voltage signals which correspond to the binary numbers O and L, the capital letter L being used to represent the number 1 in the binary system.

Two such comparison elements are shown in the periodical ETZ-A (Elektrotechnische Zeitschrift, 1958) No. 18, and ETZ-A, 1962, No. 21/22.

FIGURES 1 and 2 show comparison elements according to the prior art. Each is shown as an element capable of comparing binary numbers consisting of four binary digits, the number a having digits a a a a and the number b having digits b b b h The comparison elements have outputs at which appear the signals P N K as well as the antivalents or negated signals a o s o, s/o- When:

In each case, a negated signal will be 0 if its corresponding affirmative signal is L, and L if its corresponding affirmative signal is O.

In order to make a meaningful comparison of the circuit complexity of FIGURES 1 and 2, the circuits are so shown that passive stages are controlled only by active stages. This condition is, in practice, met for reasons of current economy. The passive stages are the AND-circuits and the OR-circuits, while the active stages are the negated or NOT-stages. The negated stages, which may, in practice, be constituted by a first transistor, are shown by the black rectangles. A further negation, effected, for example, by a second transistor which is controlled by the first transistor, is represented by the white rectangles. Each AND function is represented by the ampersand 8t and each GR function by v. Where appropriate, the & and v are indexed by means of subscripts.

In the prior art comparison element of FIGURE 1, the Signals representing the four-digit binary numbers a and b, namely, the signals a,, to a b to 12 as well as their negates E to 5 and h to 3 are applied to the AND/ NOT/NOT-circuits & to &7. The outputs of circuits & to 8: are applied to the inputs of further AND/NOT/ NOT-circuits 8: to 8: whose outputs, in turn, are. applied to the inputs of AND-circuits & to 8: The outputs of AND-circuits 8: to & are applied to the inputs of an OR/NOT/NOT-circuit v while the outputs of AND-circuits 8: to 8: are applied to another OR/NOT/ NOT-circuit v The negated outputs of v and v are applied to an AND/NOT/NOT-circuit 8: The aflirmed outputs of 81 and 8: are applied, respectively, to the respective inputs of AND-circuits 8: and 8: The circuit v plus out the signals N N the circuit v puts out the signals P F and the circuit & puts out the signals K K The comparison element according to FIGURE 2 comprises eight AND/NOT-circuits & to 8: with the circuits 8: and 8: having applied to their inputs the signals corresponding to the highest-order digits of the binary numbers, with the next AND/NOT-circuits 8: & having applied to their inputs the signals pertaining to the next-lower order digits, and so on. The stages following the stages of the highest-order digits are additionally controlled by all preceding stages. The outputs of the AND/NO'Lcircuits 8: and 8: are applied to AND/ NOT/NOT-circuits 8: and 8: at which appear the output signals P F and N K respectively. Connected to the afiirmed outputs of circuits 8: and & are the inputs of a further AND/NOT/NOT-ci-rcuit & at whose outputs appear the signals K KB The time required for forming the comparison signal is, for all practical purposes, set by the number of transistors connected in the cascade, this being represented by the white and black rectangles. For example, in the circuit of FIGURE 1, the signal K is formed after six transistor switchings, while in the circuit of FIGURE 2, the same signal is formed after eight transistor switch ings. Each of these switchings, of course, takes a certain time, so that it takes relatively long, once the input signals have been applied to the comparison element, to obtain a useful output signal which gives the desired indication.

It is, therefore the primary object of the present inventi-on to provide a comparison element which is simpler than heretofore known comparison elements and which produce the desired output signals, namely, the signals representing the existence of coincidence, i.e., equality between the numbers being compared, or the signals representing the algebraic sign of the difference between the two numbers, more quickly than do the prior art comparison elements. Accordingly, the present invention resides in a comparison element which is characterized by the following features:

(l) The numbers to be compared are divided into subnumbers or groups of digits, each of which digits is represented by a signal.

(2) The signals of each group of digits control a set of two logic input circuits. One of these puts out a single intermediate signal that indicates whether the two digit groups are coincident, i.e., equal, to each other, whereas the other of the two logic input circuits puts out a signal which indicates whether there exists a positive or negative difference between the two groups of digits.

(3) Two logic output circuits have their inputs connected to the outputs of the input circuits of each digit group for combining the intermediate results produced by each set of two input circuits.

According to a further feature of the present invention, the input circuits have their outputs connected to auxiliary logic circuits, whose outputs are connected to the above-described output circuits. That is to say, the output circuits do not have the information applied to them directly by the input circuits, instead, the set of input circuits are combined into larger groups .and have their signals passed on to the auxiliary or intermediate logic circuit, and it is the output of these auxiliary logic elements which are then applied to the final output circuits.

Additional objects and advantages of the present invention will become apparent upon consideration of the following description when taken in conjunction with the accompanying drawings in which:

FIGURES 1 and 2, already referred to above, are block diagrams of comparison elements according to the prior art.

FIGURE 3 contains block diagrams of the six logic circuits for producing the K, N and P output signals, each of which circuit is capable of handling 2-digit numbers.

FIGURE 4 contains two block diagrams of logic circuits similar to FIGURE 3 but capable of handling 3- .digit and 4-digit numbers, respectively.

FIGURE 5 contains block diagrams of logic circuits for obtaining, ultimately, the final output signals from intermediate values.

FIGURE 6 contains block diagrams of other logic circuits for producing ultimate output signals from intermediate values.

FIGURE 7 contains block diagrams of logic circuits for combining intermediate signals.

FIGURES 8 through 12 are block diagrams of comparison elements capable of handling numbers having up to 12 digits.

FIGURE 13 is a block diagram of a modified version of a part of the circuitry of FIGURE 10.

FIGURE 14 is a block diagram of a modified version of a part of the circuitry of FIGURE 12.

FIGURES 15 and 16 are block diagrams of modified versions of part of the circuitry of FIGURES and 12.

FIGURES 17 and 18 are block diagrams of modifications of the circuitryof FIGURES and 16.

FIGURE 19a is a block diagram of a part of the c0mparison element.

FIGURE 1% is a block diagram of a simplified version of the circuit of FIGURE 19a.

Before proceeding with the description of the figures, it is pointed out that, in the following description, the numbers to be compared will be considered to be the numbers a and b having digits a a a b b b with the index 0 identifying the lowest-order digit of the number, the index 1 the next higher-order digit, and so on. The digits are represented by correspondingly referenced DC. voltage signals, which are identified by O and L.

The comparison element is to determine whether a b, a b, or a=b. The numbers a and b to be compared have to be so encoded that, when a b, the binary value Binarv Totrad Representation value ofthe Decimal Encoded in Natural (each decimal digit Tetrad Number Binary Code encoded in Natural Represen- Binary Code) t tiou at the left a, 912"- LLLOOLOOOO LOOL OOOL OOLO 2,322 b, 857..." LLOLOLLOOL LOOO OLOL OLLL 2,135

The decimal number can be encoded in another suitable code, so long as the above limitation is observed.

The following applies for the comparison within each binary digit.

For the negation:

Ely=l7 (l b 1 (21 17 W,=L

The reference K represents coincidence, the reference P represents a positive deviation, i.e., a difference which, for purposes of result, will be considered a positive difference, and the reference N represents a negative difference. When groups of digits, representing a part of the number or even the entire number, are compared, the index identifies the particular part of the number with which the comparison concerns itself. If, for instance, a number consisting of digits a a a a is larger than a number consisting of digits b b b b the signal P =L. Logic functions which have been found to beparticularly advantageous for obtaining K, P and N, are set forth in the appendix, with logic functions (1) and (2) a being applicable for forming as signal for indicating coincidence or non-coincidence, as the case may be.

Circuits S and S of FIGURE 3 show how the functions may be realized, for numbers having a width of 2 bits, by using AND-circuits whose outputs are connected to the inputs of an OR/NOT-circuit. The response conditions for K are better since here the number of the individual components progresses arithmetically only and the number of inputs to each component remains constant (equal to 2).

The functions (3) and (4) are used to obtain a signal indicating positive, or non-positive, difference, with circuits S and S of FIGURE 3 showing how these functions may be realized, again for numbers having a width of 2 bits. FIGURE 4 shows two further circuits S and S each likewise consisting of AND-circuits whose outputs are connected to an OR/NOT-circuit, for realizing the from the drawing; for example, the first AND-circuit 8:

has the signals a a a 3 applied to it, and so on.

The functions (5 and (6) are used to obtain a signal indicating the negative, or non-negative, difference, with circuits S 'and S of FIGURE 3 showing how these functions may be realized.

Functions (7), (8), (9) and (10) are functions for forming the signals indicating positiveor negative differences, which functions difier. from those set forth above. These functions (7) to (10) which are realized by a chain or cascade of serially connected logic circuits, can be rewritten, for example, as functions (11) and (12) in which the solid zig-zag line representsthe switching function of a circuit which uses input AND-circuits throughout, whereas the dashed zig-zag line represents the switching function of a circuit which uses an QR/ NOT-circuit in its lowest-order digit. 2

The numbers to be comparedare divided into groups of digits. According to the present invention, the groups of digits have assigned to them input circuits which are controlled by signals a, b, these inputs circuits being arranged to produce the above switching functions. The

signals representing the intermediate results have their outputs connected to the inputs of the further circuits which form the final output result.

Functions (13), (14), (15), (16), (17) and (18)are the functions of these further circuits i.e., the auxiliary or intermediate circuits which are controlled by the signals P, N, F, F, appearing at the outputs of the circuits which themselves are controlled by the input signals a and b. The indices are shown in parentheses, this being intended to indicate that the functions apply, accordingly, in the event the individual intermediate results are each formed for a plurality of bits. For example, in the first line of function (13), the index can be replaced by the index (2/0) and the index (1) can be replaced by the index 5/3, in which case the final result would be Once the signals P, K, P, K, are available at the outputs of the logic circuits controlled by the input signals, the further logic circuits connected to these input circuits will be circuits having the switching functions and FIGURE 5 shows the circuitry for realizing the switching functions to obtain the final or ultimate output signals when there is coincidence, or positive or negative difference, from two or three, intermediate results (i.e., comparison by groups), the logic circuits being controlled by the P and N signals of the preceding logic circuits. The circuits S and S are the coincidence or K circuits, circuits S to S are the P circuits, and circuits S to S are the N circuits.

FIGURE 6 shows other logic circuits for combining intermediate results. However, the circuits of FIGURE 6 diifer from those of FIGURE 5 in that the control signals applied to them are the P and K signals, rather than the P and N signals, as was the case in FIGURE 5. Circuits S to S of FIGURE 6 are the K circuits. Circuits S to S are the P circuits, the same being controlled by the P and K output signals of the preceding logic circuits. Circuits S to S are the N circuits.

FIGURE 7 shows logic circuits S to S for the P circuit, adapted, respectively, for combining the results of 4, 5 and 6 group comparisons which produce, as intermediate results, the P and N signals.

FIGURES 8 through 12 show comparison elements for comparing numbers consisting of 12 binary digits each.

FIGURE 8 shows an element in which the intermediate results (group comparison) are formed of 4 bits each. The coincidence circuit consists of three groups S to S which are constructed in accordance with function (2). The P circuit consists of groups S to S which are constructed in accordance with function (11). Circuits S to 8, for the group comparison are controlled directly by the input signals a, b, with the circuits S to S being assigned to the four lowest-order digits, S to S being assigned to the next four digits, and S to S being assigned to the four highest of the twelve digits. In order to form the end result, the output signals of the groups of the K and P circuits are applied to circuit S operating in accordance with function (21), and to circuit S operating in accordance with function (19). The negated outputs of S and S are applied to an AND/NOT/ NOT-circuit S FIGURE 9 shows an element in which each intermediate result is constituted by 3 bits. The coincidence circuit consists of four circuits S to S operating in accordance with function (2), and the P circuit consists of circuits S to S perating in accordance with function (3). The signals representing the intermediate results again control the output circuits S and S operating in accordance with functions (21) and (19), respectively. The negated outputs of S and S are connected to the inputs of an AND/NOT/NOT-circuit S FIGURES 10, 11 and 12 show comparison elements in which the first logic input circuits, to which the signals a, b, are applied, are combined into groups of 2 bits each. In the case of the comparison elements of FIGURES 10 and 11, the intermediate results P and N are obtained at the outputs of the input circuits, while in the case of the element of FIGURE 12, the input circuits put out the intermediate results P and K. In the comparison element of FIGURE 10, P and N are derived, as final result, from the intermediate results, whereas in the comparison elements of FIGURES 11 and 12, -P and'K are first produced. The following switching functions apply:

Figure Circuit Logic Function 10 Input circuits $55-$61 (P). (4) Input circuits 862-357 (N) (5) Output circuit S (13) Output circuit S 9 (17) 11 I. Input circuits 811-515 (I?) (3) Input circuits S11-S 2 (N) (5) Output circuit Si; (13) Output circuit S (15) 12 Input circuits Sue-S91 (P) (4) Input circuits Spa- 97 (K) (2) Output circuit Sgt; (19) Output circuit Sug (21) The output circuits which are controlled directly by signals representing the intermediate results have connected to their outputs an AND/NOT/NOT-circuit S (FIGURE 10), S (FIGURE 11), S (FIGURE 12).

It will be seen that by switching the signals through in parallel, the final result is obtained very quickly. For

example, in the case of FIGURE 12, the signal K is obtained after two transistor switchings, and the signal K after three switchings.

The circuits S to S of FIGURE 10 can be replaced by a logic circuit arrangement such as is shown in FIG- URE 13. Here, further auxiliary values are formed from the intermediate values put out by the input circuits which are controlled by the input signals, this being effected by means of circuits S to S and only these auxiliary signals are applied to further logic circuits S and S to whose outputs is connected the AND/NOT/NOT-circuit S which circuits S to S put out the final results P, N and K. Thus, if the circuitry of FIGURE 13 is used in the element of FIGURE 10, the indices (0), (1), (2) and (2/()) must be replaced, respectively, by the indices l/O, 3/2, 5/4 and 5/0, and so on.

FIGURE 14 shows a circuit arrangement which can be used in place of circuits S to S of FIGURE 10. Here, too, auxiliary signals are formed from the P and K results which appear as intermediate values (circuits S to S The logic circuits S and S form, from the auxiliary signals, the final results for P and K, and the AND/NOT/NOT-circuit S forms the final signals for N.

FIGURES 15 and 16 show circuit arrangements in which, as in the case of FIGURES 13 and 14, auxiliary signals, used in forming the final output signals, are first derived from the intermediate signals produced by the input circuits, this being effected by circuits S to S in the arrangement of FIGURE 15 and by the circuits S to in the arrangement of FIGURE 16.

The circuit of FIGURE 15 can be replaced by the circuit of FIGURE 17, and the circuit of FIGURE 16 by that of FIGURE 18. The auxiliary circuits S to S in and S143 to S in 18, have applied to them the signals of the input circuits, representing the intermediate signals, have connected to their outputs further auxiliary circuits S to in FIGURE 17 and S to S in FIGURE 18. Only those signals which are put out by the last-mentioned auxiliary circuits are applied to the final output circuits.

FIGURE 19a shows, as does FIGURE 15, a circuit arrangement for that part which is connected to the input stages, without, however, being divided into auxiliary and output circuits. FIGURE 19b shows how the arrangement of FIGURE 19a can be simplified.

It will be seen from the above that the present invention resides, basically, in a comparison element for comparing multiple-digit binary numbers to determine coincidence thereof, or in the case of non-coincidence, the algebraic sign of their diiference, the numbers to be compared being divided into groups of digits each of which digits is represented by a signal. The comparison element itself comprises a plurality of logic input circuit means, cor- E 8 responding in number to the number of groups of digits into which each of the numbers to be compared is APPENDIX divided. Each set is connected to receive the Signals which [Logic functims] represent the digits that are part of the two groups of 60 8:50 (an &bD) Ko (1) digits to be compared by the respective set. Each set f 5 (E & E0 & a & 51) V (an & b0 & E1 & 51) V (in & so & a1 & b1) v (M & b0 input circuit means has first and second input circuits, 8w! &bx)=K1/0 the first input circuit indicating coincidence of the two 3,, & & 5, 5, & E, 3, E v (a0 3; be & 3 & B & 5 a; 5, v 3,, & 5, 5; groups of digits and the second input circuit indicating a a1 & b1 & E1 & E) v (30 & b0 & a1 & 13161 El & El) v (3 & E0 & 1 a: El positive or negative difference between the two groups of & a; & D!) v (20 e & 1 1 61 2 & 2) v (E0 & Eu & at & b1 & a: 8: digits. Output circuit means are provided for combining 10 b2) a1&b1& am b2)=K2/ the outputs of the input circuit means, these output cir- (2) cuit means including a first output circuit which iscon- (a0 & 50) v (30 8:130:30 nected to receive the outputs of all of the first input (amwvgm (H &B' E & K circuits of all of the sets for combining the same, and a e 5, v(E &b )v(a & 5 v (5 &b1) v (and: E) v (528: bZ)=K2/0 second output circuit which is connected to receive the outputs of all of the second input circuits of all of the (3) sets for combining the same. (80 & Eu)= o a t (811 & hi) V (at & 3o dz Bo) V (E1 & 9.0 dz Bu)=P1/n 36333155 l iiii iiiifiiteifrfi is ii tiifiihiiitii e a e s a v a a s M s & a & it v & a

e a dzbi)v(bz&ai&ao&h )v (b2&B1&ao&bo)=P2lo control art, in which a machine tool is controlled numerr- 2O cally in accordance with a predetermined program so that (4) the actual work tool, e.g., a milling cutter, will be made 30 v 130:?) to follow a given path with respect to a work piece. It" (E &E )v(?i &b )v(E &bn)v(b &o)v(bi&b )=P1 the work piece is clamped in place, the tool will be made (Tm&b2)V(3285515850)V(2&E1&b0)V(E2&E1&b1) V616: b1 & Euyv to move relative to the bed of the machine. The actual $3z&br&bu)V(b2&1&110)V(bt&31&b0) vcflt'slaldlbl) V(b2&b1&' position of the work tool relative to the work piece is measured by suitable photosensitive scanning means, which may incorporate digitally coded scales so that the scanning means produces, as its output, a digital number EZ") (l 0 N which represents the actual position of the work tool. 2 V f 3 This number is compared with the nominal position of the g gfig gg 3fg;fi & M V (hast m work tool, i.e., the position which the work tool should 1 v a m M 0 V Z 1 an m occupy relative to the work piece as dictated by the (6) program. This nominal position may itself be expressed aWEFN-O as a digital number. The digital numbers representing, a pvm als yB B,& E,&B respectively, the actual and the nominal position of the (am 52) v (art: 4 at) v (ai 2.16: Fe) v (am ant: 51) v (at & B1 & an) v work tool relative to the work piece, and which, in prac- 5 W (526: m &a1&FO)V 2 1 & 1) v 1 tice, may have some twenty digits each, are then com- &a)v(b&E1&E)=m/ pared with each other. If they are equal, the position of d the work tool is in agreement with the position dictated (7) by the program. if the numbers are not equal to each 222g; :31 6181)? (P0 &B] =Pm other, the work tool 18 not in agreement With. tne pro- (3,;&E:)V(P1/0&313)V(P1/0&E2)=P2' l0 grammed position and has to be advanced or retarded. (gammy(Pm&a3)v(P,,o&5,)=Pm This is accomplished by applying the appropriate control signal to the machine control system, and this signal is (8) 'that put out by, or derived from, the comparison element 30v bo= F which compares the two numbers. It is for this reason that 1 & 1) v o & 51) v (F06: b1)= 1/o the algebraic sign of the difierence is significant, because, (Fl/05151) (Pl/03 depending on whether the actual position is, numerically, v (EM QMPFEN greater or smaller than the programmed or nominal position, the tool will be advanced or retarded. &b (9) It will be understood that the above description of the g: & 3 (Doro & 51) V (Nu & 130:1 present invention 1s susceptible to various modifications, (528,132) v (NI/(1&5?) V (NHDLQMFNZN changes, and adaptations, and the same are intended to (5mm) v (Ni/Maia) v 2/o a)= s/o be comprehended within the meaning and range of equivalents of the appended claims. For example the present (10) invention is not limited to the precise application deaovEn=No scribed above which is given only by way of example, as (318 E V Q & 31) V (F131 5 L there are many other cases, in industrial 'and scientific (am 1 V Ed V Fl IPFNZN fields, where two digital numbers have to be compared. (a3 & b3) V (Mm & as) v (NM &

a :fi 7 D \qp GOV-5J0 :Po fii Qv zP 5e52,)! 5 8:5 =2 9K '6 Q5 i" i. 0 i qxfia hb wg M1)V\P9 &b, V0 (a sent-rt? sage a, as, =15 1 2 s b a) /o a 2/0 f a a /s fi q )=1= o) V u) & m) V o) & n) & 2))= (2/o) m V o) & m) V u) m & Km) V (PM) 0) m 61 o) V o) & Kw) V o) & m & m) V o) & m & m &

m) V w) & Km 61 Km K(s )=N(a/o) m) v Kn) V o om m) v Kn) V m V m m What is claimed is:

1. In a digital comparison element for comparing two series of signals which represent numbers, which series of signals are arranged in multiple-digit signal groups, there being first means for testing whether or not there is coincidence of signal representation of said numbers and forming a first intermediate signal, second means for testing the algebraic sign of the difference between said signal representations of said numbers and forming a second intermediate signal, said first and second means being constituted, respectively, by two logic input circuits which each signal group has associated with it and which input circuits are controlled by the signals of the respective signal group, there further being third means for putting out a coincidence signal and an algebraic sign signal, said third means being constituted by two logic output circuits which are controlled by the intermediate signals of all of said logic input circuits, wherein the improvement comprises the arrangement that each signal group encompasses two or three binary digits and each logic input circuit for testing for coincidence has, for each binary digit of the signal group, two input AND- circuits which are controlled by the signals of the respective signal group, there being OR/NOT-circuit means for combining the output signals of all of said AND-circuits into said first intermediate signal; said improvement further comprising the arrangement that the logic input circuit which pertains to the signal group and which is provided for testing the algebraic sign of the difference has input AND circuits whose number is determined by the number of binary digits of the signal group, there being OR/NOT circuit means for combining the output signals of all of said last-mentioned AND- circuits into said second intermediate signal.

References Cited UNITED STATES PATENTS 2,885,655 5/1959 Smoliar 34'0--l49 MALCOLM A. MORRISON, Primary Examiner. K. F. MILDE, V. SIBER, Assistant Examiners. 

1. IN A DIGITAL COMPARISON ELEMENT FOR COMPARING TWO SERIES OF SIGNALS WHICH REPRESENT NUMBERS, WHICH SERIES OF SIGNALS ARE ARRANGED IN MULTI-DIGIT SIGNAL GROUPS, THERE BEING FIRST MEANS FOR TESTING WHETHER OR NOT THERE IS COINCIDENCE OF SIGNAL REPRESENTATION OF SAID NUMBERS AND FORMING A FIRST INTERMEDIATE SIGNAL, SECOND MEANS FOR TESTING THE ALGEBRAIC SIGN OF THE DIFFERENCE BETWEEN SAID SIGNAL REPRESENTATIONS OF SAID NUMBERS AND FORMING A SECOND INTERMEDIATE SIGNAL, SAID FIRST AND SECOND MEANS BEING CONSTITUTED, RESPECTIVELY, BY TWO LOGIC INPUT CIRCUITS WHICH EACH SIGNAL GROUP HAS ASSOCIATED WITH IT AND WHICH INPUT CIRCUITS ARE CONTROLLED BY THE SIGNALS OF THE RESPECTIVE SIGNAL GROUP, THERE FURTHER BEING THIRD MEANS FOR PUTTING OUT A COINCIDENCE SIGNAL AND AN ALGEBRAIC SIGN SIGNAL, SAID THIRD MEANS BEING CONSTITUTED BY TWO LOGIC OUTPUT CIRCUITS WHICH ARE CONTROLLED BY THE INTERMEDIATE SIGNALS OF ALL OF SAID LOGIC INPUT CIRCUITS, WHEREIN THE IMPROVEMENT COMPRISES THE ARRANGEMENT THAT EACH SIGNAL GROUP ENCOMPASS TWO OR THREE BINARY DIGITS AND EACH LOGIC INPUT CIRCUIT FOR TESTING FOR COINCIDENCE HAS, FOR EACH BINARY DIGIT OF THE SIGNAL GROUP, TWO INPUT ANDCIRCUITS WHICH ARE CONTROLLED BY THE SIGNALS OF THE RESPECTIVE SIGNAL GROUP, THERE BEING OR/NOT-CIRCUIT MEANS FOR COMBINING THE OUTPUT SIGNALS OF ALL OF SAID AND-CIRCUITS INTO SAID FIRST INTERMEDIATE SIGNAL; SAID IMPROVEMENT FURTHER COMPRISING THE ARRANGEMENT THAT THE LOGIC INPUT CIRCUIT WHICH PERTAINS TO THE SIGNAL GROUP AND WHICH IS PROVIDED FOR TESTING THE ALGEBRAIC SIGN OF THE DIFFERENCE HAS INPUT AND-CIRCUITS WHOSE NUMBER IS DETERMINED BY THE NUMBER OF BINARY DIGITS OF THE SIGNAL GROUP, THERE BEING OR/NOT CIRCUIT MEANS FOR COMBINING THE OUTPUT SIGNALS OF ALL OF SAID LAST-MENTIONED ANDCIRCUITS INTO SAID SECOND INTERMEDIATE SIGNAL. 